1995 microchip technology inc. ds11183c-page 1 24c01a/02a/04a features low power cmos technology hardware write protect two wire serial interface bus, i 2 c ? compatible 5 volt only operation self-timed write cycle (including auto-erase) page-write buffer 1ms write cycle time for single byte 1,000,000 erase/write cycles guaranteed data retention >200 years 8-pin dip/soic packages available for extended temperature ranges: - commercial: 0?c to +70?c - industrial: -40?c to +85?c - automotive: -40?c to +125?c description the microchip technology inc. 24c01a/02a/04a is a 1k/2k/4k bit electrically erasable prom. the device is organized as shown, with a standard two wire serial interface. advanced cmos technology allows a signif- icant reduction in power over nmos serial devices. a special feature in the 24C02A and 24c04a provides hardware write protection for the upper half of the block. the 24c01a and 24C02A have a page write capability of two bytes and the 24c04a has a page length of eight bytes. up to eight 24c01a or 24C02A devices and up to four 24c04a devices may be con- nected to the same two wire bus. this device offers fast (1ms) byte write and extended (-40 c to 125 c) temperature operation. it is recommended that all other applications use microchip s 24lcxxb. 24c01a 24C02A 24c04a organization 128 x 8 258 x 8 2 x 256 x 8 write protect none 080-0ff 100-1ff page write buffer 2 bytes 2 bytes 8 bytes package type block diagram 1
2
3
4 8
7
6
5 a0
a1
a2
v ss v
wp*
scl
sda cc 1
2
3
4 8
7
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5 v
wp*
scl
sda cc a0
a1
a2
v ss nc ss cc a0 a1 nc a2 nc v 1 2 3 4 5 6 7 14 13 12 nc scl sda nc 9 8 11 10 wp v nc dip 8-lead soic 14-lead soic * ?est?pin in 24c01a 24c01a 24C02A 24c04a 24c01a 24C02A 24c04a 24c01a 24C02A 24c04a r/w amp v pp a
d
d
r
e
s
s p
o
i
n
t
e
r memory
array
slave addr. data reg. data
buffer
(fif0) control
logic sda v cc v ss scl a0 to
a7 increment a8 a1 a2 a0 wp 1k/2k/4k 5.0v cmos serial eeproms i 2 c is a trademark of phillips corporation
24c01a/02a/04a ds11183c-page 2 1995 microchip technology inc. 1.0 electrical characteristics 1.1 maximum ratings* v cc ........................................................................ 7.0v all inputs and outputs w.r.t. v ss .....-0.6v to v cc +1.0v storage temperature ...........................-65?c to +150?c ambient temp. with power applied ......-65?c to +125?c soldering temperature of leads (10 seconds) ...+300?c esd protection on all pins..................................... 4 kv *notice: stresses above those listed under ?aximum ratings may cause permanent damage to the device. this is a stress rat- ing only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this speci?ation is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. table 1-1: pin function table name function a0 no function for 24c04a only, must be connected to v cc or v ss a0, a1, a2 chip address inputs v ss ground sda serial address/data i/o scl serial clock test (24c01a only) v cc or v ss wp write protect input v cc +5v power supply table 1-2: dc characteristics figure 1-1: bus timing start/stop v cc = +5v ( 10%) commercial (c): tamb = 0?c to +70?c industrial (i): tamb = -40?c to +85?c automotive (e): tamb = -40 c to +125 c parameter symbol min. max. units conditions v cc detector threshold v th 2.8 4.5 v scl and sda pins: high level input voltage low level input voltage low level output voltage v ih v il v ol v cc x 0.7 -0.3 v cc + 1 v cc x 0.3 0.4 v v vi ol = 3.2 ma (sda only) a1 & a2 pins: high level input voltage low level input voltage v ih v il v cc - 0.5 -0.3 v cc + 0.5 0.5 v v input leakage current i li ?0 m av in = 0v to v cc output leakage current i lo ?0 m av out = 0v to v cc pin capacitance (all inputs/outputs) c in , c out 7.0 pf v in /v out = 0v (note 1) tamb = +25?c, f = 1 mhz operating current i cc write 3.5 ma f clk = 100 khz, program cycle time = 1 ms, vcc = 5v, tamb = 0?c to +70?c i cc write 4.25 ma f clk = 100 khz, program cycle time = 1 ms, vcc = 5v, tamb = (i) and (e) i cc read 750 m av cc = 5v, tamb= (c), (i) and (e) standby current i ccs 100 m a sda=scl=v cc =5v (no program active) note 1: this parameter is periodically sampled and not 100% tested. scl sda start stop t su:sta t hd:sta t su:sto
1995 microchip technology inc. ds11183c-page 3 24c01a/02a/04a table 1-3: ac characteristics figure 1-2: bus timing data parameter symbol min. typ max. units remarks clock frequency f clk 100 khz clock high time t high 4000 ns clock low time t low 4700 ns sda and scl rise time t r 1000 ns sda and scl fall time t f 300 ns start condition hold time t hd :s ta 4000 ns after this period the ?st clock pulse is generated start condition setup time t su :s ta 4700 ns only relevant for repeated start condition data input hold time t hd :d at 0 ns data input setup time t su :d at 250 ns data output delay time t aa 300 3500 note 1 stop condition setup time t su :s to 4700 ns bus free time t buf 4700 ns time the bus must be free before a new transmission can start input ?ter time constant (sda and scl pins) t i 100 ns program cycle time t wc .4 1 ms byte mode .4n n ms page mode, n=# of bytes note 1: as transmitter the device must provide this internal minimum delay time to bridge the unde?ed region (minimum 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. su:sta t hd:sta t f t low t high t r t su:sto t buf t t aa t sda out sda in scl hd:dat t su:dat t aa
24c01a/02a/04a ds11183c-page 4 1995 microchip technology inc. 2.0 functional description the 24c01a/02a/04a supports a bidirectional two wire bus and data transmission protocol. a device that sends data onto the bus is de?ed as transmitter, and a device receiving data as receiver. the bus has to be controlled by a master device which generates the serial clock (scl), controls the bus access, and gener- ates the start and stop conditions, while the 24c01a/02a/04a works as slave. both master and slave can operate as transmitter or receiver but the master device determines which mode is activated. up to eight 24c01/24c02s can be connected to the bus, selected by the a0, a1 and a2 chip address inputs. up to four 24c04as can be connected to the bus, selected by a1 and a2 chip address inputs. a0 must be tied to v cc or v ss for the 24c04a. other devices can be con- nected to the bus but require different device codes than the 24c01a/02a/04a (refer to section slave address). 3.0 bus characteristics the following bus protocol has been de?ed: data transfer may be initiated only when the bus is not busy. during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as a start or stop condition. accordingly, the following bus conditions have been de?ed (see figure 3-1). 3.1 bus not busy (a) both data and clock lines remain high. 3.2 start data t ransfer (b) a high to low transition of the sda line while the clock (scl) is high determines a start condition. all commands must be preceded by a start condi- tion. 3.3 stop data t ransfer (c) a low to high transition of the sda line while the clock (scl) is high determines a stop condition. all operations must be ended with a stop condition. 3.4 data v alid (d) the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. the number of the data bytes transferred between the start and stop conditions is determined by the master device and is theoretically unlimited. 3.5 acknowledge each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. the master device must generate an extra clock pulse which is associated with this acknowledge bit. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave must leave the data line high to enable the master to generate the stop condition. note: the 24c01a/02a/04a does not generate any acknowledge bits if an internal pro- gramming cycle is in progress. figure 3-1: data transfer sequence on the serial bus scl sda (a) (b) (d) (d) (c) (a) start condition address
or
acknowledge
valid data allowed
to change stop
condition
1995 microchip technology inc. ds11183c-page 5 24c01a/02a/04a 4.0 slave address the chip address inputs a0, a1 and a2 of each 24c01a/ 02a/04a must be externally connected to either v cc or ground (v ss ), assigning to each 24c01a/02a/04a a unique address. a0 is not used on the 24c04a and must be connected to either v cc or v ss . up to eight 24c01a or 24C02A devices and up to four 24c04a devices may be connected to the bus. chip selection is then accomplished through software by setting the bits a0, a1 and a2 of the slave address to the corresponding hard-wired logic levels of the selected 24c01a/02a/ 04a. after generating a start condition, the bus mas- ter transmits the slave address consisting of a 4-bit device code (1010) for the 24c01a/02a/04a, followed by the chip address bits a0, a1 and a2. in the 24c04a, the seventh bit of that byte (a0) is used to select the upper block (addresses 100?ff) or the lower block (addresses 000?ff) of the array. the eighth bit of slave address determines if the master device wants to read or write to the 24c01a/02a/04a (see figure 4-1). the 24c01a/02a/04a monitors the bus for its corre- sponding slave address all the time. it generates an acknowledge bit if the slave address was true and it is not in a programming mode. figure 4-1: slave address allocation 5.0 byte program mode in this mode, the master sends addresses and one data byte to the 24c01a/02a/04a. following the start signal from the master, the device code (4-bits), the slave address (3-bits), and the r/w bit, which is logic low, are placed onto the bus by the master. this indicates to the addressed 24c01a/02a/ 04a that a byte with a word address will follow after it has generated an acknowledge bit. therefore the next byte transmitted by the master is the word address and will be written into the address pointer of the 24c01a/ 02a/04a. after receiving the acknowledge of the 24c01a/02a/04a, the master device transmits the data word to be written into the addressed memory location. the 24c01a/02a/04a acknowledges again and the master generates a stop condition. this initiates the internal programming cycle of the 24c01a/02a/04a (see figure 6-1). start read/write slave address r/w 1 0 1 0 a2a1a0 a 6.0 page program mode to program the 24c01a/02a/04a, the master sends addresses and data to the 24c01a/02a/04a which is the slave (see figure 6-1 and figure 6-2). this is done by supplying a start condition followed by the 4-bit device code, the 3-bit slave address, and the r/w bit which is de?ed as a logic low for a write. this indi- cates to the addressed slave that a word address will follow so the slave outputs the acknowledge pulse to the master during the ninth clock pulse. when the word address is received by the 24c01a/02a/04a, it places it in the lower 8 bits of the address pointer de?ing which memory location is to be written. (the a0 bit transmitted with the slave address is the ninth bit of the address pointer for the 24c04a). the 24c01a/02a/ 04a will generate an acknowledge after every 8-bits received and store them consecutively in a ram buffer until a stop condition is detected. this stop condi- tion initiates the internal programming cycle. the ram buffer is 2 bytes for the 24c01a/02a and 8 bytes for the 24c04a. if more than 2 bytes are transmitted by the master to the 24c01a/02a, the device will not acknowl- edge the data transfer and the sequence will be aborted. if more than 8 bytes are transmitted by the master to the 24c04a, it will roll over and overwrite the data beginning with the ?st received byte. this does not affect erase/write cycles of the eeprom array and is accomplished as a result of only allowing the address registers bottom 3 bits to increment while the upper 5 bits remain unchanged. if the master generates a stop condition after trans- mitting the ?st data word (point ? on figure 6-1), byte programming mode is entered. the internal, completely self-timed program cycle starts after the stop condition has been generated by the master and all received data bytes in the page buffer will be written in a serial manner. the program cycle takes n milliseconds, whereby n is the number of received data bytes (n max = 8 for 24c04a, 2 for 24c01a/02a).
24c01a/02a/04a ds11183c-page 6 1995 microchip technology inc. figure 6-1: byte write figure 6-2: page write s
t
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p sda line p data s
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byte s word
address bus activity:
master bus activity: a
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address (n) bus activity:
master bus activity: a
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k 7.0 acknowledge polling since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). once the stop condition for a write com- mand has been issued from the master, the device ini- tiates the internally timed write cycle. ack polling can be initiated immediately. this involves the master sending a start condition followed by the control byte for a write command (r/w = 0). if the device is still busy with the write cycle, then no ack will be returned. if the cycle is complete, then the device will return the ack and the master can then proceed with the next read or write command. see figure 7-1 for ?w dia- gram. figure 7-1: acknowledge polling flow send
write command send stop
condition to
initiate write cycle send start send control byte
with r/w = 0 did device
acknowledge
(ack = 0)? next
operation no yes
1995 microchip technology inc. ds11183c-page 7 24c01a/02a/04a 8.0 write protection programming of the upper half of the memory will not take place if the wp pin of the 24C02A or 24c04a is connected to v cc (+5v). the device will accept slave and word addresses but if the memory accessed is write protected by the wp pin, the 24C02A/04a will not generate an acknowledge after the ?st byte of data has been received, and thus the program cycle will not be started when the stop condition is asserted. polarity of the wp pin has no effect on the 24c01a. 9.0 read mode this mode illustrates master device reading data from the 24c01a/02a/04a. as can be seen from figure 9-2 and figure 9-3, the master ?st sets up the slave and word addresses by doing a write. (note: although this is a read mode, the address pointer must be written to). during this period the 24c01a/02a/04a generates the necessary acknowledge bits as de?ed in the appropriate section. the master now generates another start condition and transmits the slave address again, except this time the read/write bit is set into the read mode. after the slave generates the acknowledge bit, it then outputs the data from the addressed location on to the sda pin, increments the address pointer and, if it receives an acknowledge from the master, will transmit the next consecutive byte. this auto-increment sequence is only aborted when the master sends a stop condition instead of an acknowledge. note 1: if the master knows where the address pointer is, it can begin the read sequence at the current address (see figure 9-1) and save time transmitting the slave and word addresses. note 2: in all modes, the address pointer will not increment through a block (256 byte) boundary, but will rotate back to the ?st location in that block. figure 9-1: current address read figure 9-2: random read sda line s
t
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byte s data n bus activity:
master bus activity: a
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24c01a/02a/04a ds11183c-page 8 1995 microchip technology inc. figure 9-3: sequential read s
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p sda line data n data n + 1 bus activity:
master bus activity: a
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k 10.0 pin description 10.1 a0, a1, a2 chip address inputs the levels on these inputs are compared with the cor- responding bits in the slave address. the chip is selected if the compare is true. for 24c04 a0 is no function. up to eight 24c01a/02a's or up to four 24c04a's can be connected to the bus. these inputs must be connected to either v ss or v cc . 10.2 sda serial address/data input/output this is a bidirectional pin used to transfer addresses and data into and data out of the device. it is an open drain terminal, therefore the sda bus requires a pull-up resistor to v cc (typical 10k w ). for normal data transfer, sda is allowed to change only during scl low. changes during scl high are reserved for indicating the start and stop condi- tions. 10.3 scl serial clock this input is used to synchronize the data transfer from and to the device. 10.4 wp w rite protection this pin must be connected to either v cc or v ss for 24C02A or 24c04a. it has no effect on 24c01a. if tied to v cc , program operations onto the upper memory block will not be executed. read operations are possible. if tied to v ss , normal memory operation is enabled (read/write the entire memory). this feature allows the user to assign the upper half of the memory as rom which can be protected against accidental programming. when write is disabled, slave address and word address will be acknowledged but data will not be acknowledged. note 1: a ?age?is de?ed as the maximum num- ber of bytes that can be programmed in a single write cycle. the 24c04a page is 8 bytes long; the 24c01a/02a page is 2 bytes long. note 2: a ?lock?is de?ed as a continuous area of memory with distinct boundaries. the address pointer can not cross the bound- ary from one block to another. it will how- ever, wrap around from the end of a block to the ?st location in the same block. the 24c04a has two blocks, 256 bytes each. the 24c01a and 24C02A each have only one block.
1995 microchip technology inc. ds11183c-page 9 24c01a/02a/04a notes
24c01a/02a/04a ds11183c-page 10 1995 microchip technology inc. 24c01a/02a/04a product identi cation system to order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed sales of?es. package: p = plastic dip sn = plastic soic (150 mil body), 8-lead sm = plastic soic (207 mil body), 8-lead sl = plastic soic (150 mil body), 14-lead, 24c04a only temperature blank = 0 c to +70 c range: i = -40 c to +85 c e = -40 c to +125 c device: 24c01a 1k cmos serial eeprom 24c01at 1k cmos serial eeprom (tape and reel) 24C02A 2k cmos serial eeprom 24C02At 2k cmos serial eeprom (tape and reel) 24c04a 4k cmos serial eeprom 24c04at 4k cmos serial eeprom (tape and reel) 24c01a/02a/04a - /p americas (continued) san jose microchip technology inc. 2107 north first street, suite 590 san jose, ca 95131 tel: 408 436-7950 fax: 408 436-7955 asia/pacific hong kong microchip technology unit no. 3002-3004, tower 1 metroplaza 223 hing fong road kwai fong, n.t. hong kong tel: 852 2 401 1200 fax: 852 2 401 3431 korea microchip technology 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku, seoul, korea tel: 82 2 554 7200 fax: 82 2 558 5934 singapore microchip technology 200 middle road #10-03 prime centre singapore 188980 tel: 65 334 8870 fax: 65 334 8850 taiwan microchip technology 10f-1c 207 tung hua north road taipei, taiwan, roc tel: 886 2 717 7175 fax: 886 2 545 0139 europe united kingdom arizona microchip technology ltd. unit 6, the courtyard meadow bank, furlong road bourne end, buckinghamshire sl8 5aj tel: 44 0 1628 851077 fax: 44 0 1628 850259 france arizona microchip technology sarl 2 rue du buisson aux fraises 91300 massy - france tel: 33 1 69 53 63 20 fax: 33 1 69 30 90 79 germany arizona microchip technology gmbh gustav-heinemann-ring 125 d-81739 muenchen, germany tel: 49 89 627 144 0 fax: 49 89 627 144 44 italy arizona microchip technology srl centro direzionale colleoni palazzo pegaso ingresso no. 2 via paracelso 23, 20041 agrate brianza (mi) italy tel: 39 039 689 9939 fax: 39 039 689 9883 japan microchip technology intl. inc. benex s-1 6f 3-18-20, shin yokohama kohoku-ku, yokohama kanagawa 222 japan tel: 81 45 471 6166 fax: 81 45 471 6122 9/5/95 americas corporate of?e microchip technology inc. 2355 west chandler blvd. chandler, az 85224-6199 tel: 602 786-7200 fax: 602 786-7277 technical support: 602 786-7627 web: http://www.mchip.com/biz/mchip atlanta microchip technology inc. 500 sugar mill road, suite 200b atlanta, ga 30350 tel: 770 640-0034 fax: 770 640-0307 boston microchip technology inc. 5 mount royal avenue marlborough, ma 01752 tel: 508 480-9990 fax: 508 480-8575 chicago microchip technology inc. 333 pierce road, suite 180 itasca, il 60143 tel: 708 285-0071 fax: 708 285-0075 dallas microchip technology inc. 14651 dallas parkway, suite 816 dallas, tx 75240-8809 tel: 214 991-7177 fax: 214 991-8588 dayton microchip technology inc. 35 rockridge road englewood, oh 45322 tel: 513 832-2543 fax: 513 832-2841 los angeles microchip technology inc. 18201 von karman, suite 455 irvine, ca 92715 tel: 714 263-1888 fax: 714 263-1338 new york microchip technology inc. 150 motor parkway, suite 416 hauppauge, ny 11788 tel: 516 273-5305 fax: 516 273-5335 "information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. no representation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents arising from such use or otherwise. use of microchip's products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, under any intellectual property rights." the microchip logo and name are registered trademarks of microchip technology inc. all rights reserved. all other trademarks mentioned herein are the property of their respective companies. printed in the usa, 9/95 1995, microchip technology incorporated
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